1. Field of the Invention
Present invention relates to electromigration analysis and specifically to electromigration analysis of signal nets in an integrated circuit.
2. Description of the Related Art
Generally, integrated circuit designs are becoming more complex and denser. More devices are compressed in the integrated circuits to improve the performance; however, the currents in these devices typically remain comparable despite increasing miniaturization of the integrated circuits. With higher current density, integrated circuits become more susceptible to electromigration causing the circuits to fail.
Modern integrated circuits typically include a dense array of narrow metallic conductors that carry current between various devices on the chip. At high current densities the electron momentum is transferred to the atoms in these thin film metallic conductors (e.g. signal nets) causing a net atomic flux. The atomic flux leads to voids which can cause a circuit to break open or hillocks, e.g., accumulation of metal leading to shorts with adjacent metal lines (signal nets). These and other effects are generally referred to as electromigration. During the circuit design, it is important to determine the electromigration risk of signal nets in the integrated circuit.
Various tools are available to estimate the current density and electromigration risk of signal nets in the integrated circuits. However, these tools typically require final layout of the integrated circuit and that the layout be free of power and ground shorts. Typically, the clean final layout is not available until the later part of the design cycle. Thus, it becomes difficult to make appropriate adjustment in the design without adding considerable amount of delays (in some cases, months) to the design cycle. Further, the accuracy calculated by these tools is typically within 20% of the actual current density. This leads to inaccurate design of current density for signal nets. A method and apparatus is needed to accurately determine the current density and electromigration risks of signal nets in the integrated circuit earlier in the design cycle.